SPWM波發(fā)生器VHDL語言正弦波脈寬調(diào)制quartus仿真

名稱：SPWM波發(fā)生器VHDL語言正弦波脈寬調(diào)制（代碼在文末下載）

軟件：Quartus II

語言：VHDL

代碼功能：

完成基于FPGA的SPWM發(fā)生器的設(shè)計，輸出1路SPWM信號。

實現(xiàn)的方法：分別產(chǎn)生正弦波和三角波，將正弦波和三角波進行比較，三角波大于正弦波時輸出1，否則輸出0

FPGA代碼Verilog/VHDL代碼資源下載：www.hdlcode.com

演示視頻：

設(shè)計文檔：

1. 工程文件

2. 程序文件

3. 程序編譯

4. RTL圖

5. Testbench

6. 仿真圖

相位累加器模塊

三角波ROM模塊

正弦波ROM模塊

部分代碼展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
???USE?ieee.std_logic_unsigned.all;
ENTITY?Sweep_frequency?IS
???PORT?(
??????clk?????????????:?IN?STD_LOGIC;--時鐘
??????PWM_wave????????:?OUT?STD_LOGIC--輸出PWM波形
???);
END?Sweep_frequency;
ARCHITECTURE?behavioral?OF?Sweep_frequency?IS
COMPONENT?sin_ROM?IS
PORT
(
address:?IN?STD_LOGIC_VECTOR?(9?DOWNTO?0);
clock:?IN?STD_LOGIC??:=?'1';
q:?OUT?STD_LOGIC_VECTOR?(9?DOWNTO?0)
);
END?COMPONENT;
COMPONENT?triangle_ROM?IS
PORT
(
address:?IN?STD_LOGIC_VECTOR?(9?DOWNTO?0);
clock:?IN?STD_LOGIC??:=?'1';
q:?OUT?STD_LOGIC_VECTOR?(9?DOWNTO?0)
);
END?COMPONENT;
???COMPONENT?Freq_sum?IS
??????PORT?(
?????????clk?????????????:?IN?STD_LOGIC;
?????????freq_data???????:?IN?STD_LOGIC_VECTOR(9?DOWNTO?0);
?????????freq_out????????:?OUT?STD_LOGIC_VECTOR(9?DOWNTO?0)
??????);
???END?COMPONENT;
???
???SIGNAL?freq_out_sin??:?STD_LOGIC_VECTOR(9?DOWNTO?0);
???SIGNAL?q_sin?????????:?STD_LOGIC_VECTOR(9?DOWNTO?0);--ROM輸出波形
???SIGNAL?freq_out_triangle??:?STD_LOGIC_VECTOR(9?DOWNTO?0);
???SIGNAL?q_triangle?????????:?STD_LOGIC_VECTOR(9?DOWNTO?0);--ROM輸出波形
BEGIN
???
???
???--sin存儲Rom表
???i_sin_ROM?:?sin_ROM
??????PORT?MAP?(
?????????address??=>?freq_out_sin,--查找表地址
?????????clock????=>?clk,--時鐘
?????????q????????=>?q_sin--輸出波形
??????);
???--triangle存儲Rom表
???i_triangle_ROM?:?triangle_ROM
??????PORT?MAP?(
?????????address??=>?freq_out_triangle,--查找表地址
?????????clock????=>?clk,--時鐘
?????????q????????=>?q_triangle--輸出波形
??????);
???
???--相位累加器
???i0_Freq_sum?:?Freq_sum
??????PORT?MAP?(
?????????clk????????=>?clk,
?????????freq_data??=>?"0000000001",--頻率控制字10bit----
?????????freq_out???=>?freq_out_sin--累加器輸出
??????);
???--相位累加器
???i1_Freq_sum?:?Freq_sum
??????PORT?MAP?(
?????????clk????????=>?clk,
?????????freq_data??=>?"0000011000",--頻率控制字10bit----
?????????freq_out???=>?freq_out_triangle--累加器輸出
??????);
PWM_wave<='1'?when?freq_out_triangle>freq_out_sin?else?'0';--三角波大于正弦波時輸出1，否則輸出0
END?behavioral;

點擊鏈接獲取代碼文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=271