8位二進(jìn)制硬件乘加器VHDL代碼 DE0開發(fā)板KX-CDS-CV5實驗箱

名稱：8位二進(jìn)制硬件乘加器（代碼在文末下載）

軟件：QuartusII

語言：VHDL

代碼功能：

8位二進(jìn)制硬件乘加器

要求:yout= a0 x b0+a1 x b1;

ao、bo、a1、b1均為8位二進(jìn)制有符號數(shù),能同時顯示乘數(shù)、被乘數(shù) 積的信息(LED數(shù)碼管)。

本代碼已在DE0-CV開發(fā)板，KX-CDS-CV5實驗箱驗證成功，開發(fā)板及實驗箱如下：

FPGA代碼Verilog/VHDL代碼資源下載：www.hdlcode.com

部分代碼展示

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
--頂層模塊
ENTITY?mult?IS
???PORT?(
??????clk????????:?IN?STD_LOGIC;---時鐘
??????rst_p??????:?IN?STD_LOGIC;--復(fù)位--實驗箱鍵1
??????data_in????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);--二進(jìn)制輸入--核心板SW0~7，SW設(shè)置8位2進(jìn)制有符號數(shù)，然后按key_a0就將該數(shù)輸入到程序中，key_b0，key_a1，key_b1類似
??????key_a0?????:?IN?STD_LOGIC;--a0按鍵--核心板key0
??????key_b0?????:?IN?STD_LOGIC;--b0按鍵--核心板key1
??????key_a1?????:?IN?STD_LOGIC;--a1按鍵--核心板key2
??????key_b1?????:?IN?STD_LOGIC;--b1按鍵--核心板key3
??????key_enter??:?IN?STD_LOGIC;--計算按鍵--實驗箱鍵2
??????
--實驗箱數(shù)碼管顯示端口
??????a0_H???????:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0);
??????a0_L???????:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0);
??????b0_H???????:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0);
??????b0_L???????:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0);
??????a1_H???????:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0);
??????a1_L???????:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0);
??????b1_H???????:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0);
??????b1_L???????:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0);
??????--核心板數(shù)碼管顯示端口
??????HEX0???????:?OUT?STD_LOGIC_VECTOR(6?DOWNTO?0);
??????HEX1???????:?OUT?STD_LOGIC_VECTOR(6?DOWNTO?0);
??????HEX2???????:?OUT?STD_LOGIC_VECTOR(6?DOWNTO?0);
??????HEX3???????:?OUT?STD_LOGIC_VECTOR(6?DOWNTO?0)
???);
END?mult;
ARCHITECTURE?behave?OF?mult?IS
???COMPONENT?display?IS
??????PORT?(
?????????a0?????????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????b0?????????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????a1?????????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????b1?????????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????result?????:?IN?STD_LOGIC_VECTOR(15?DOWNTO?0);
?????????a0_H???????:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0);
?????????a0_L???????:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0);
?????????b0_H???????:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0);
?????????b0_L???????:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0);
?????????a1_H???????:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0);
?????????a1_L???????:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0);
?????????b1_H???????:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0);
?????????b1_L???????:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0);
?????????HEX0???????:?OUT?STD_LOGIC_VECTOR(6?DOWNTO?0);
?????????HEX1???????:?OUT?STD_LOGIC_VECTOR(6?DOWNTO?0);
?????????HEX2???????:?OUT?STD_LOGIC_VECTOR(6?DOWNTO?0);
?????????HEX3???????:?OUT?STD_LOGIC_VECTOR(6?DOWNTO?0)
??????);
???END?COMPONENT;
COMPONENT?mult_ctrl?IS
???PORT?(
??????clk????????:?IN?STD_LOGIC;
??????rst_p??????:?IN?STD_LOGIC;
??????data_in????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
??????key_a0?????:?IN?STD_LOGIC;
??????key_b0?????:?IN?STD_LOGIC;
??????key_a1?????:?IN?STD_LOGIC;
??????key_b1?????:?IN?STD_LOGIC;
??????key_enter??:?IN?STD_LOGIC;
??????a0_o?????????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
??????b0_o?????????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
??????a1_o?????????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
??????b1_o?????????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
??????result_o?????:?OUT?STD_LOGIC_VECTOR(15?DOWNTO?0)
???);
END?COMPONENT;
???
???
???SIGNAL?a0??????????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?b0??????????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?a1??????????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?b1??????????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?result??????:?STD_LOGIC_VECTOR(15?DOWNTO?0);
???
BEGIN
?--調(diào)用控制模塊
???i_mult_ctrl?:?mult_ctrl
??????PORT?MAP?(
?????????clk????????=>?clk,
?????????rst_p??????=>?rst_p,
?????????data_in????=>?data_in,
?????????key_a0?????=>?key_a0,
?????????key_b0?????=>?key_b0,
?????????key_a1?????=>?key_a1,
?????????key_b1?????=>?key_b1,
?????????key_enter??=>?key_enter,
?????????a0_o?????????=>?a0,
?????????b0_o?????????=>?b0,
?????????a1_o?????????=>?a1,
?????????b1_o?????????=>?b1,
?????????result_o?????=>?result
??????);
???
???
???--調(diào)用顯示模塊
???i_display?:?display
??????PORT?MAP?(
?????????a0??????=>?a0,
?????????b0??????=>?b0,
?????????a1??????=>?a1,
?????????b1??????=>?b1,
?????????result??=>?result,
?????????
?????????a0_H????=>?a0_H,
?????????a0_L????=>?a0_L,
?????????b0_H????=>?b0_H,
?????????b0_L????=>?b0_L,
?????????a1_H????=>?a1_H,
?????????a1_L????=>?a1_L,
?????????b1_H????=>?b1_H,
?????????b1_L????=>?b1_L,
?????????
?????????HEX0????=>?HEX0,
?????????HEX1????=>?HEX1,
?????????HEX2????=>?HEX2,
?????????HEX3????=>?HEX3
??????);
???
END?behave;

點擊鏈接獲取代碼文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=230