RS232接口數(shù)據(jù)發(fā)送UART串口協(xié)議Verilog代碼Quartus仿真

名稱：RS232接口數(shù)據(jù)發(fā)送UART串口協(xié)議Verilog代碼Quartus仿真

軟件：Quartus

語言：Verilog

代碼功能：

設(shè)計RS232接口數(shù)據(jù)轉(zhuǎn)發(fā)協(xié)議,將8位并行數(shù)據(jù)轉(zhuǎn)發(fā)為RS232協(xié)議的串口數(shù)據(jù)發(fā)送出去。

entity rs232

port(clk: in std_ logic;--16MHz輸入時鐘

rdy: in std logic;-數(shù)據(jù)準備好信號,1個時鐘周期的正脈沖

data: in std logic vecton(7 downto0);--要發(fā)送的并行數(shù)據(jù)

bps: in std logic_ vector( I downto0):--波特率設(shè)置

00:9600bps01:1920010:38400

d_out: out std_ logic);-串行數(shù)據(jù)輸出

end rs232.

協(xié)議要求：

(1)波特率:9600/19200/38400可選；

(2)8位數(shù)據(jù)位,1為停止位,偶校驗。

設(shè)計要求:

(1)采用VHDL或 Verilog語言設(shè)計上述電路；

(2)寫出測試激勵文件,并仿真；

(3)分析仿真結(jié)果,并撰寫設(shè)計報告；

(4)提交完整的電子版設(shè)計報告并附源代碼。

FPGA代碼Verilog/VHDL代碼資源下載：www.hdlcode.com

演示視頻：

設(shè)計文檔：

1. 工程文件

2. 程序文件

3. 程序編譯

4. Testbench

5. 仿真圖

部分代碼展示:

module?rs232(
????input??????clk,??????????????????//系統(tǒng)時鐘16MHz
????input?????????rst_n,????????????????//系統(tǒng)復(fù)位，低電平有效
????input?????????rdy,??????????????????//數(shù)據(jù)準備好信號，1時鐘周期正脈沖
????input??[7:0]??data,?????????????????//待發(fā)送并行數(shù)據(jù)
?input??[1:0]??bps,??????????????????//波特率設(shè)置,00:9600bps?01:19200?10:38400
????output??reg???d_out?????????????????//串行數(shù)據(jù)輸出
????);
//parameter?define
parameter??CLK_FREQ?=?16000000;?????????????//系統(tǒng)時鐘頻率16MHz
reg?[31:0]?UART_BPS?=?9600;?????????????????//串口波特率
always?@(posedge?clk?or?negedge?rst_n)?????????
????if?(!rst_n)?
UART_BPS<=9600;
?else
case(bps)
2'b00:UART_BPS<=9600;//9600bps
2'b01:UART_BPS<=19200;//19200bps
2'b10:UART_BPS<=38400;//38400bps
default:;
endcase
wire?[31:0]?BPS_CNT;//為得到指定波特率，對系統(tǒng)時鐘計數(shù)BPS_CNT次
assign?BPS_CNT??=?CLK_FREQ/UART_BPS;????//為得到指定波特率，對系統(tǒng)時鐘計數(shù)BPS_CNT次
//reg?define
reg????????uart_en_d0;?
reg????????uart_en_d1;??
reg?[15:0]?clk_cnt;?????????????????????????//系統(tǒng)時鐘計數(shù)器
reg?[?3:0]?tx_cnt;??????????????????????????//發(fā)送數(shù)據(jù)計數(shù)器
reg????????tx_flag;?????????????????????????//發(fā)送過程標志信號
reg?[?7:0]?tx_data;?????????????????????????//寄存發(fā)送數(shù)據(jù)
//wire?define
wire???????en_flag;
//*****************************************************
//**????????????????????main?code
//*****************************************************
//捕獲uart_en上升沿，得到一個時鐘周期的脈沖信號
assign?en_flag?=?(~uart_en_d1)?&?uart_en_d0;
?????????????????????????????????????????????????
//對發(fā)送使能信號uart_en延遲兩個時鐘周期
always?@(posedge?clk?or?negedge?rst_n)?begin?????????
????if?(!rst_n)?begin
????????uart_en_d0?<=?1'b0;??????????????????????????????????
????????uart_en_d1?<=?1'b0;
????end??????????????????????????????????????????????????????
????else?begin???????????????????????????????????????????????
????????uart_en_d0?<=?rdy;???????????????????????????????
????????uart_en_d1?<=?uart_en_d0;????????????????????????????
????end
end
//當脈沖信號en_flag到達時,寄存待發(fā)送的數(shù)據(jù)，并進入發(fā)送過程??????????
always?@(posedge?clk?or?negedge?rst_n)?begin?????????
????if?(!rst_n)?begin??????????????????????????????????
????????tx_flag?<=?1'b0;
????????tx_data?<=?8'd0;
????end?
????else?if?(en_flag)?begin?????????????????//檢測到發(fā)送使能上升沿??????????????????????
????????????tx_flag?<=?1'b1;????????????????//進入發(fā)送過程，標志位tx_flag拉高
????????????tx_data?<=?data;????????????//寄存待發(fā)送的數(shù)據(jù)
????????end
????????else?
????????if?((tx_cnt?==?4'd10)&&(clk_cnt?==?BPS_CNT/2))
????????begin???????????????????????????????//計數(shù)到停止位中間時，停止發(fā)送過程
????????????tx_flag?<=?1'b0;????????????????//發(fā)送過程結(jié)束，標志位tx_flag拉低
????????????tx_data?<=?8'd0;
????????end
????????else?begin
????????????tx_flag?<=?tx_flag;
????????????tx_data?<=?tx_data;
????????end?
end
//進入發(fā)送過程后，啟動系統(tǒng)時鐘計數(shù)器與發(fā)送數(shù)據(jù)計數(shù)器
always?@(posedge?clk?or?negedge?rst_n)?begin?????????
????if?(!rst_n)?begin?????????????????????????????
????????clk_cnt?<=?16'd0;??????????????????????????????????
????????tx_cnt??<=?4'd0;
????end??????????????????????????????????????????????????????
????else?if?(tx_flag)?begin?????????????????//處于發(fā)送過程
????????if?(clk_cnt?<?BPS_CNT?-?1)?begin
????????????clk_cnt?<=?clk_cnt?+?1'b1;
????????????tx_cnt??<=?tx_cnt;
????????end
????????else?begin
????????????clk_cnt?<=?16'd0;???????????????//對系統(tǒng)時鐘計數(shù)達一個波特率周期后清零
????????????tx_cnt??<=?tx_cnt?+?1'b1;???????//此時發(fā)送數(shù)據(jù)計數(shù)器加1
????????end
????end
????else?begin??????????????????????????????//發(fā)送過程結(jié)束
????????clk_cnt?<=?16'd0;
????????tx_cnt??<=?4'd0;
????end

點擊鏈接獲取代碼文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=530