洗衣機(jī)控制器VHDL代碼Quartus DE2-115開(kāi)發(fā)板

名稱：洗衣機(jī)控制器VHDL代碼Quartus? DE2-115開(kāi)發(fā)板

軟件：Quartus

語(yǔ)言：VHDL

代碼功能：

洗衣機(jī)控制器：

（1）設(shè)計(jì)一個(gè)洗衣機(jī)控制器，使洗衣機(jī)作如下運(yùn)轉(zhuǎn)：定時(shí)啟動(dòng)—〉正轉(zhuǎn)20秒—〉暫停10秒—〉反轉(zhuǎn)20秒—〉暫停10秒—〉定時(shí)不到，重復(fù)上面過(guò)程。

（2）若定時(shí)到，則停止，并發(fā)出提示信號(hào)。

（3）用兩個(gè)數(shù)碼管顯示洗滌的預(yù)置時(shí)間（分鐘數(shù)），按倒計(jì)時(shí)方式對(duì)洗滌過(guò)程作計(jì)時(shí)顯示，直到時(shí)間到停機(jī)；洗滌過(guò)程由開(kāi)始信號(hào)開(kāi)始。

（4）三只LED燈表示正轉(zhuǎn)、反轉(zhuǎn)、暫停三個(gè)狀態(tài)。

FPGA代碼Verilog/VHDL代碼資源下載：www.hdlcode.com

本代碼已在DE2-115開(kāi)發(fā)板驗(yàn)證，DE2-115開(kāi)發(fā)板如下，其他開(kāi)發(fā)板可以修改管腳適配：

設(shè)計(jì)文檔：

洗衣機(jī)程序設(shè)計(jì)

1. 工程文件

2. 程序文件

3. 程序編譯

4. RTL圖

5. 管腳分配

6. 仿真圖

洗滌預(yù)制時(shí)間寄存模塊

時(shí)序電路模塊

十進(jìn)制減法計(jì)數(shù)模塊

譯碼器驅(qū)動(dòng)電路模塊

部分代碼展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
???USE?ieee.std_logic_unsigned.all;
ENTITY?washing_machine?IS
???PORT?(
??????clk_in?????:?IN?STD_LOGIC;--50Hz
??????start_key??:?IN?STD_LOGIC;--啟動(dòng)按鍵
??????
??????set_time_key:?IN?STD_LOGIC?;--預(yù)置時(shí)間按鍵，按一次增加5分鐘，超過(guò)60分鐘自動(dòng)回零
??????
??????led????????:?OUT?STD_LOGIC_VECTOR(2?DOWNTO?0);--正轉(zhuǎn)，反轉(zhuǎn)，暫停
??????end_led????:?OUT?STD_LOGIC;--洗衣結(jié)束信號(hào)
??????
??????dig_led1????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);--數(shù)碼管1
??????dig_led2???:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)--數(shù)碼管2
???);
END?washing_machine;
ARCHITECTURE?Behavioral?OF?washing_machine?IS
--洗滌預(yù)制時(shí)間寄存模塊/十進(jìn)制減法計(jì)數(shù)模塊/時(shí)序電路模塊/譯碼器驅(qū)動(dòng)電路模塊/數(shù)碼管顯示模塊???
--洗滌預(yù)制時(shí)間寄存模塊
Component?pre_set_time?IS
PORT?(
clk_in?????:?IN?STD_LOGIC;--50Hz?????
set_time_key:?IN?STD_LOGIC?;--預(yù)置時(shí)間按鍵，按一次增加5分鐘，超過(guò)60分鐘自動(dòng)回零
preset_time????:??OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)
);
end?Component?;
--譯碼器驅(qū)動(dòng)電路模塊
Component?decoder?IS
PORT?(
clk_in?:?IN?STD_LOGIC?;
washing_time?:?IN?STD_LOGIC_VECTOR?(7?downto?0);
duanxuan2??:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
duanxuan1??:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)
);
end?Component?;
--數(shù)碼管顯示模塊
Component?display?IS
PORT?(
duanxuan2??:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
duanxuan1??:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
dig_led1????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);--數(shù)碼管1
dig_led2???:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)--數(shù)碼管2
);
end?Component?;
Component?subtraction?IS
PORT?(
clk_in??:?IN?STD_LOGIC;--50Hz
start_key_rise??:?IN?STD_LOGIC;
min_en_rise????:?IN?STD_LOGIC;
preset_time????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
washing_time???:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)
);
end?Component?;
Component?Sequential_circuit?IS
PORT?(
clk_in?????:?IN?STD_LOGIC;--50Hz
start_key??:?IN?STD_LOGIC;--啟動(dòng)按鍵
washing_time???:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);??????
led????????:?OUT?STD_LOGIC_VECTOR(2?DOWNTO?0);--正轉(zhuǎn)，反轉(zhuǎn)，暫停
end_led????:?OUT?STD_LOGIC;--洗衣結(jié)束信號(hào)
??????
start_key_rise_out????:?OUT?STD_LOGIC;
min_en_rise_out???:?OUT?STD_LOGIC
);
end?Component?;
???SIGNAL?preset_time????:??STD_LOGIC_VECTOR(7?DOWNTO?0):=?"00000000";
???SIGNAL?washing_time????????:?STD_LOGIC_VECTOR(7?DOWNTO?0)?:=?"00000000";--預(yù)置洗衣時(shí)間15分鐘
???
???SIGNAL?start_key_rise??????:?STD_LOGIC:='0';
???SIGNAL?min_en_rise?????????:?STD_LOGIC:='0';???
???
???SIGNAL?duanxuan2?????????????:?STD_LOGIC_VECTOR(7?DOWNTO?0)?:=?"00000000";
???SIGNAL?duanxuan1????????????:?STD_LOGIC_VECTOR(7?DOWNTO?0)?:=?"00000000";
BEGIN

點(diǎn)擊鏈接獲取代碼文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=557