名稱:簡易波形發(fā)生器VHDL代碼Quartus仿真
軟件:Quartus
語言:VHDL
代碼功能:
簡易波形發(fā)生器
2、通過開關(guān)控制輸出哪種類型。
FPGA代碼Verilog/VHDL代碼資源下載:www.hdlcode.com
演示視頻:
設計文檔:
1. 工程文件
2. 程序文件
3. 原理圖
4. 程序編譯
5. RTL圖
6. 仿真圖
部分代碼展示:
LIBRARY?ieee; ???USE?ieee.std_logic_1164.all; ???USE?ieee.std_logic_unsigned.all; ENTITY?wave_generation?IS ???PORT?( ??????sys_clk?????????:?IN?STD_LOGIC;--輸入時鐘???? ??????wave_select?????:?IN?STD_LOGIC_VECTOR(1?DOWNTO?0);--波形選擇 ??????wave_data?????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)--波形輸出 ???); END?wave_generation; ARCHITECTURE?behaviour?OF?wave_generation?IS ???--波形發(fā)生模塊 COMPONENT?carrier_wave?IS ??????PORT?( ?????????clk?????????????:?IN?STD_LOGIC; ?????????triangular_wave?:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0); ?????????square_wave?????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0); ?????????sin_wave????????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0) ??????); ???END?COMPONENT; --3選1模塊,00輸出0;01-方波;10-三角波;11-正弦波,wave_select控制3選1 COMPONENT?MUX_31?IS ???PORT?( ?????????triangular_wave?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0); ?????????square_wave?????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0); ?????????sin_wave????????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0); ?????????wave_select?????:?IN?STD_LOGIC_VECTOR(1?DOWNTO?0); ?????????wave_data???????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)--波形輸出 ???); END?COMPONENT; ???SIGNAL?triangular_wave???:?STD_LOGIC_VECTOR(7?DOWNTO?0); ???SIGNAL?square_wave?????:?STD_LOGIC_VECTOR(7?DOWNTO?0); ???SIGNAL?sin_wave????????:?STD_LOGIC_VECTOR(7?DOWNTO?0); BEGIN
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