FPGA的數(shù)字鐘校時鬧鐘報時VHDL代碼

名稱：基于FPGA的數(shù)字鐘具有校時鬧鐘報時功能（代碼在文末付費下載）

軟件：Quartus

語言：VHDL

要求：

1、計時功能:這是數(shù)字鐘設(shè)計的基本功能，每秒鐘更新一次,并且能在顯示屏上顯示當前的時間。
2、鬧鐘功能:如果當前的時間與鬧鐘設(shè)置的時間相同,則揚聲器發(fā)出鬧音。
3、校時設(shè)置:用戶可以通過功能鍵重新進行時間設(shè)置.精確校時時還可以對秒進行清零。
4、整點報功能:如果當前時間為整點，則揚聲器發(fā)出特定頻率的整點報音。
5、鬧鈴設(shè)置:用戶可以通過功能鍵完成任意時間的鬧鈴設(shè)置。
6、顯示功能:正常計時狀態(tài)6位數(shù)碼管分別顯示時、分、秒;校時狀態(tài)顯示時、分、鬧鐘設(shè)置狀態(tài)顯示當前鬧鐘的時分設(shè)置值。

本課題要達到的目標是:在Quartus?II軟件上用VHDL語言編寫相關(guān)的應用程序，利用FPGA完成數(shù)字時鐘，使其功能基本得到實現(xiàn)。

部分代碼展示

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
ENTITY?Digital_clock?IS
???PORT?(
??????clk_50M?????:?IN?STD_LOGIC;
??????key_0???????:?IN?STD_LOGIC;--模式設(shè)置按鍵--4'd0:計時，4'd1：鬧鐘，4'd3:溫度
??????key_1???????:?IN?STD_LOGIC;--設(shè)置修改
??????key_2???????:?IN?STD_LOGIC;--修改確認
??????key_3???????:?IN?STD_LOGIC;--修改時分秒,鬧鐘關(guān)閉
???one_wire????:?INOUT?STD_LOGIC;??--?傳感器One-Wire總線
??????
??????bell_out????:?OUT?STD_LOGIC;
??????led_mode????:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0);--led顯示當前模式
??????bit_select??:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);--數(shù)碼管位選
??????seg_select??:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)--數(shù)碼管段選
???);
END?Digital_clock;
ARCHITECTURE?behave?OF?Digital_clock?IS
--模塊聲明
???--響鈴模塊
???COMPONENT?Bell?IS
??????PORT?(
?????????clk_50M?????:?IN?STD_LOGIC;
?????????clear_alarm?:?IN?STD_LOGIC;
?????????alarm_hour_time?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????alarm_minute_time?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????alarm_second_time?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????hour_time???:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????minute_time?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????second_time?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????bell_out????:?OUT?STD_LOGIC
??????);
???END?COMPONENT;
???--鬧鐘模塊
???COMPONENT?alarm_clock?IS
??????PORT?(
?????????clk_50M?????:?IN?STD_LOGIC;
?????????state_mode??:?IN?STD_LOGIC_VECTOR(3?DOWNTO?0);
?????????set_time_key?:?IN?STD_LOGIC;
?????????confirm_key?:?IN?STD_LOGIC;
?????????change_time_key?:?IN?STD_LOGIC;
?????????alarm_hour_time?:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????alarm_minute_time?:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????alarm_second_time?:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)
??????);
???END?COMPONENT;
???--顯示模塊
???COMPONENT?display?IS
??????PORT?(
?????????clk?????????:?IN?STD_LOGIC;
?????????state_mode??:?IN?STD_LOGIC_VECTOR(3?DOWNTO?0);
temperature?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);--溫度
?????????alarm_hour_time?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????alarm_minute_time?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????alarm_second_time?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????hour_time???:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????minute_time?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????second_time?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????bit_select??:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????seg_select??:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)
??????);
???END?COMPONENT;
???--設(shè)置模式
???COMPONENT?set_mode?IS
??????PORT?(
?????????clk_50M?????:?IN?STD_LOGIC;
?????????set_mode_key?:?IN?STD_LOGIC;
?????????led_mode????:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0);
?????????state_mode??:?OUT?STD_LOGIC_VECTOR(3?DOWNTO?0)
??????);
???END?COMPONENT;
???--分頻模塊
???COMPONENT?fenping?IS
??????PORT?(
?????????clk_50M?????:?IN?STD_LOGIC;
?????????clk_1Hz?????:?OUT?STD_LOGIC
??????);
???END?COMPONENT;
???--按鍵消抖
???COMPONENT?key_jitter?IS
??????PORT?(
?????????clkin???????:?IN?STD_LOGIC;
?????????key_in??????:?IN?STD_LOGIC;
?????????key_negedge?:?OUT?STD_LOGIC
??????);
???END?COMPONENT;
???--計時模塊
???COMPONENT?jishi?IS
??????PORT?(
?????????clk_50M?????:?IN?STD_LOGIC;
?????????clk_1Hz?????:?IN?STD_LOGIC;
?????????state_mode??:?IN?STD_LOGIC_VECTOR(3?DOWNTO?0);
?????????set_time_key?:?IN?STD_LOGIC;
?????????confirm_key?:?IN?STD_LOGIC;
?????????change_time_key?:?IN?STD_LOGIC;
?????????hour_time???:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????minute_time?:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????second_time?:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)
??????);
???END?COMPONENT;
COMPONENT?ds18B20?is??
port(
clk?:?in?std_logic;???--為50MHz?
dq??:?inout?std_logic;??
LED?:?out?std_logic;?
LED2?:?out?std_logic;?
LED3?:?out?std_logic;?
rst:?in?std_logic;?
temp_h:out?std_logic_vector(7?downto?0);
temp_l:out?std_logic_vector(7?downto?0)
);??
end?COMPONENT;?
???SIGNAL?state_mode????????????:?STD_LOGIC_VECTOR(3?DOWNTO?0);--當前模式，4'd0:計時，4'd1：鬧鐘，4'd2:跑表
???SIGNAL?hour_time?????????????:?STD_LOGIC_VECTOR(7?DOWNTO?0);--時
???SIGNAL?minute_time???????????:?STD_LOGIC_VECTOR(7?DOWNTO?0);--分
???SIGNAL?second_time???????????:?STD_LOGIC_VECTOR(7?DOWNTO?0);--秒
???SIGNAL?alarm_hour_time???????:?STD_LOGIC_VECTOR(7?DOWNTO?0);--鬧鐘時
???SIGNAL?alarm_minute_time?????:?STD_LOGIC_VECTOR(7?DOWNTO?0);--鬧鐘分
???SIGNAL?alarm_second_time?????:?STD_LOGIC_VECTOR(7?DOWNTO?0);--鬧鐘秒
???
???SIGNAL?key_0_negedge?????????:?STD_LOGIC;--按鍵下降沿
???SIGNAL?key_1_negedge?????????:?STD_LOGIC;--按鍵下降沿
???SIGNAL?key_2_negedge?????????:?STD_LOGIC;--按鍵下降沿
???SIGNAL?key_3_negedge?????????:?STD_LOGIC;--按鍵下降沿
???
???SIGNAL?clk_1Hz???????????????:?STD_LOGIC;--1Hz

仿真圖(文檔點擊可下載)：

1. 分頻模塊

2. 設(shè)置鬧鐘模塊

3. 響鈴模塊包括鬧鐘和整點報時

4. display顯示模塊

5. 計時模塊

6. 模式設(shè)置模塊

7. 按鍵模塊

8. 整體仿真

本代碼已在開發(fā)板驗證，開發(fā)板資料如下：

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